Recently, since demands for a flash memory greatly increase in consumer electronics and mobile electronic apparatuses, a market of the flash memory is expected to continuously increase. In addition, demands for a cell device having a high integration density, a high durability, and high-speed write/erase characteristics have been increased. Particularly, the integration degree of a NAND flash memory has been required to continuously increase as IT technologies are developed. The integration density of the NAND flash memory greatly depends on the integration density of the cell devices. Recently, the gate length of a cell device is reduced down to 50 nm, and the memory capacity reaches several tens of giga bits. In addition, demands for multi-level cell devices have been increased. However, the short channel effect due to device miniaturization increases dispersion of a threshold voltage in the implementation of the multi-level cell, the device miniaturization of the multi-level cell may be limitatively used, or it cannot be used. In order to improve the integration density, the gate length needs to be continuously reduced. Therefore, other techniques have to be considered.
In a conventional NAND flash memory using floating gates, serious problems of cross-talk between cells occur as cell miniaturization proceeds. In order to increase the integration density of a conventional device having a floating poly electrode, an SONOS flash memory cell that uses an insulating storage electrode such as nitride layer as a memory storage node has been considered. In addition, a nano-floating gate memory (NFGM) cell that uses nano-sized dots or nano-sized crystals as a storage electrode has been considered. In a case where a memory cell is embodied by using a storage electrode such as nano-sized dots or a nitride layer on a conventional planar channel structure, miniaturization characteristics can be improved in comparison with a case where a memory cell is embodied by using a conventional conductive polysilicon floating gate. However, although the improved storage electrode is used, in a case where the gate length is equal to or less than 30 nm, the characteristics are greatly deteriorated, or the miniaturization may not be obtained due to the short channel effect.
In order to suppress the short channel effect caused in a case where a gate length of a cell device decreases below 40 nm and reduce a dispersion of a threshold voltage, an SONOS or TANOS (TaN—AlO—SiN-Oxide-Si) cell device having an asymmetric source/drain structure on a planar channel device is proposed by Samsung Electronics Co., Ltd (K. T. Park et al, A 64-cell NAND flash memory with asymmetric S/D structure for sub-40 nm technology and beyond, in Technical Digest of Symposium on VLSI Technology, p. 24, 2006). The aforementioned the cell device has a structure where, with respect to a gate of the cell device, there is a region corresponding to a source or a drain in the one side thereof, and there is neither source nor drain in the other side thereof. In the cell device having the structure, the short channel effect is suppressed by forming an inversion layer using a fringe field from a control electrode in the region where there is neither source nor drain. Although the miniaturization characteristic of the cell device is improved in comparison with a conventional SONOS the cell device having a planar channel and a source/drain region, since one of the source and the drain of the cell device is formed so as to be overlapped with the control electrode, the short channel effect occurs in the channel length equal to or less than 40 nm. As a result, there is a limitation in miniaturization of the cell device having a flat channel structure.
A flash device structure in which a channel is recessed and a conductive floating gate is used as a storage electrode so as to reduce the short channel effect occurring in the conventional planar channel structure is proposed by Samsung Electronics Co., Ltd. (S.-P. Sim et al, Full 3-dimensional NOR flash cell with recessed channel and cylindrical floating gate—A scaling direction for 65 nm and beyond, in Technical Digest of Symposium on VLSI Technology, p. 22, 2006). However, in the flash device having such a structure, the width of the recessed region needs to be reduced as the device miniaturization proceeds. Accordingly, there is a problem in that device characteristics deteriorate, and non-uniformity of the device increases.
The inventor has researched a NAND string structure having no source/drain, and the invention titled, “Highly-Integrated Flash Memory Cell String, Cell Device, and Method of Fabricating thereof” was filed and registered as Korean Patent No. 10-856701. With respect to the structure disclosed in the invention, the process of fabricating a NAND string is simple, and there is no source/drain in the cell device, so that it is possible to improve device miniaturization characteristics, program characteristics, and the like. Herein, although the cell device has no source/drain, the cell device is based on a MOS structure having a channel. Therefore, a new cell device structure which does not employ the MOS structure is needed.
A result of research of implementing memory operations by reading GIDL (Gate Induced Drain Leakage) in a FinFET-based SONOS flash memory, of which the device miniaturization characteristics are good, at the level of a single cell device was published (Alvaro Padilla et al., Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method, in Technical Digest of Symposium on VLSI Technology, p. 143, 2008). Since the cell device is also based on the cell having a MOS structure, there are problems such as problems in the processes of fabricating a miniaturized MOS device and problems of a change in a threshold voltage.
In this manner, development of new cell devices and cell strings capable of solving the problems of the previously proposed devices, simplifying the fabricating processes, and increasing a integration density and performance has been required.